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#i nclude "msp430x11x1.h" ;"STD_DEF.ASM" ;Stack SECT 00300h ROM_orig set 0F000h RAM_orig set 00200h Main equ ROM_orig RXD set 004h ;P2.2 CCI0B input TXD set 002h ;P1.1 Out0 output ;RXTXData EQU R5 BITCNT EQU 210H ;BitCnt EQU R6 BITIME EQU 14 BITIME_5 EQU 6
;----------------------------------------------------------------- ORG 0F000H
;------------------------------------------------------------------ RESET mov #300H,SP call #Init_Sys Mainloop mov.b #55h,R5 ;;;;;寻址方式:符号模式。RXTXData用上了吗 call #TX_Byte call #RX_READY bis #LPM0,SR ;;;;;CPUOFF,LPM3行吗 ;call #TX_Byte jmp Mainloop
;----------------------------------------------------------------- TX_Byte ;------------------------------------------------------------------ MOV &TAR,&CCR0 ADD #BITIME,&CCR0 BIS #0100H,R5 RLA R5 MOV #10,&BITCNT MOV #OUTMOD0+CCIE,&CCTL0 TX_WAIT BIT #CCIE,&CCTL0 JNZ TX_WAIT RET RX_READY MOV #08,&BITCNT SETUPRX MOV #CCIS0+OUTMOD0+CM1+CAP+CCIE,&CCTL0 RET
;---------------------------------------------------------------- TAInt0 ;---------------------------------------------------------------- ADD #BITIME,&CCR0 BIT #CCIS0,&CCTL0 JNZ UART_RX UART_TX bic #OUTMOD2,&CCTL0 RRA R5 JC TX_TEST TX_SPACE bis #OUTMOD2,&CCTL0 TX_TEST DEC &BITCNT JNZ TX_NEXT BIC #CCIE,&CCTL0 TX_NEXT RETI UART_RX BIT #CAP,&CCTL0 JZ RX_BIT RX_EDGE BIC #CAP,&CCTL0 ADD #BITIME_5,&CCR0 RETI RX_BIT BIT #SCCI,&CCTL0 RRC.B R5 RX_TEST DEC &BITCNT JNZ RX_NEXT RX_COMP MOV.B R5,&220H BIC #CCIE,&CCTL0 MOV #GIE,0(SP) RX_NEXT RETI
;-------------------------------------------------------------- Init_Sys ;------------------------------------------------------------- mov #WDTPW+WDTHOLD,&WDTCTL ;关看门狗 SetupBC ;bis.b #XTS,&BCSCTL1 ;Basic clock system control1 57H ;;;;XTS=1,LFXT1工作在高频模式,实际晶振也要对应上 ;bis.b #SELM1+SELM0,&BCSCTL2 ;Basic clock system control2 58H ;MCLK=LFXT1CLK SetupTA mov #TASSEL0+MC1,&TACTL ;ACLK。连续增计数
SetupC0 mov #OUT,&CCTL0 ;;;;如果选择输出模式0,则由OUTx位确定OUTx信号 SetupP1_2 bis.b #TXD,&P1SEL ;外围模块功能 bis.b #TXD,&P1DIR ;输出模式 bis.b #RXD,&P2SEL ;外围模块功能 eint ret
;-------------------------------------------------------------- RSEG INTVEC ;-------------------------------------------------------------- DW RESET DW RESET DW RESET DW RESET DW RESET DW RESET DW RESET DW RESET DW RESET DW TAInt0 DW RESET DW RESET DW RESET DW RESET DW RESET DW RESET ;--------------------------------------------------------------------------------------------------- END
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